MIL-PRF-83531C
3.4.6 Passive circuit elements. Capacitors shall be qualified or screened to MIL-PRF-55681.
Resistors shall be qualified or screened to MIL-PRF-55342. The inductor shall be so designed as to
allow the delay line to meet the requirements specified herein.
3.4.7 Magnet wire. Magnet wire, when used shall be selected to enable the part to meet the
requirements of this specification. Additional information and guidance on magnet wire is provided in 6.6.
3.4.8 Pure tin. Use of pure tin, plating or otherwise, is prohibited internally and externally (see 6.9).
Use of tin-lead finishes are acceptable provided that the minimum lead continent is 3 percent.
Acceptance or approval of any constituent material shall not be construed as a guaranty of the
acceptance of the finished product (see 4.6.1).
3.5 Interface and physical dimensions. Delay lines shall meet the interface and physical dimensions
specified (see 3.1), and shall meet all performance requirements and product characteristics specified
herein.
3.5.1 Dimensions. When delay lines are inspected in accordance with 4.6.2, the dimensions shall be
within the tolerances specified on the applicable specification sheet (see 3.1).
3.5.2 Visual inspection. When delay lines are inspected in accordance with 4.6.3, they shall not exhibit
flaking, pitting, blistering, peeling, cracks, bursting, bulging, or other defects. The delay lines shall also
meet the requirements of 3.1, 3.22, and 3.23.
3.6 Thermal shock. When delay lines are tested as specified in 4.6.4, not more than 10 percent of the
surface shall have peeling, flaking, chipping, cracking, or other impairment of the protective finish; no
evidence of other physical damage such as cracks, bursting, or bulging of the case; or other defects that
would affect the mechanical or electrical operation, and there shall be no electrical discontinuity.
3.7 Seal. When delay lines are tested as specified in 4.6.5 there shall be no evidence of continuous air
bubble flow or compound leakage.
3.8 Electrical characteristics. Delay lines shall be capable of meeting all the electrical requirements
specified (see 3.1 and 3.8.1 through 3.8.8).
3.8.1 Delay time. When tested in accordance with 4.6.6.1.1, the overall specified delay time of the line
shall be as specified. The input-to-tap and tap-to-sequential tap shall be as specified (see 3.1).
3.8.2 Rise time. When measured in accordance with 4.6.6.1.2, the rise time of pulses taken at the
point of maximum delay shall not exceed the value specified (see 3.1). The rise time measured at the
taps shall not exceed the rise time required at the point of maximum delay.
3.8.3 Voltage attenuation. When measured in accordance with 4.6.6.1.3, the voltage attenuation of
pulses taken at the point of maximum delay with respect to the input pulse amplitude shall not exceed the
value specified (see 3.1). The voltage attenuation measured at the taps shall not exceed the voltage
attenuation required at the point of maximum delay.
3.8.4 Distortion. Unless otherwise specified (see 3.1), when measured in accordance with 4.6.6.1.4,
the all encompassing distortion of pulses appearing at the point of maximum delay shall not exceed ±15
percent.
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